Karim Bigou
karim.bigou@univ-brest.fr
Département Informatique U.F.R. Sciences et Techniques, Université de Bretagne
Occidentale, 20 avenue Le Gorgeu C.S. 93837, 29238 BREST Cedex 3, France
(+33) (0)2 98 01 67 97
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Current Position
Since September 2016, I am assistant professor at Université de
Bretagne Occidentale in the computer science
department. I do my research in the ARCAD team of the
SHARP department of Lab-STICC laboratory, working on computer arithmetic for
cryptographic implementations, in hardware (FPGA) and software (multicore processors).
Teaching
Since September 2021, I am in charge of the 2nd year of the computer science bachelor (licence in
french) of Université de Bretagne Occidentale (UBO).
I am currently teaching in the computer science
departement of UBO the following courses:
- C Programming (2nd year)
- Computer Architecture and Operating Systems (2nd year)
- Cyber Security (Embedded System and Software) (5th year)
Formerly teached at UBO:
- Introduction to Algorithmics (lecture by D. Massé)
- Java Programming (lecture by M. Kerboeuf)
I did various courses (vacations) in 2014-2016 at IUT Lannion in the DUT Informatique
about Operating Systems, Computer Architecture, Network Architecture, Object-oriented programming or
Algorithmics and C Programming.
Research
Current Research Interests
- Applied Cryptography and Security:
- FPGA accelerators
- public key cryptography
- side-channel attacks, fault injection attacks and countermeasures
- fast software implementations
- Computer Arithmetic:
- finite field arithmetic
- residue number systems (RNS)
- high-performance computations
- Hardware Operators
- Hardware and Software Implementations:
- Software Parallel implementations (multi-core with OpenMP)
- Hardware Implementations (FPGA, Embedded Systems)
- trade-off speed/area/energy
PhD Students
- Morgane Vollmer (last year), Software RNS support for homomorphic encryption on
parallel processors, UBO Lab-STICC (grant DGA-PEC), advisors: L. Nana, A. Tisserand and K. Bigou
- Emilie Debelle (1st year), Agile and Secure Cryptographic Accelerators, CNRS
Lab-STICC (grant ARSENE Project), advisors: A. Tisserand and
K. Bigou
- Bastien Maffre (1st year), FPGA accelerators using RNS arithmetic for Isogenies
between Elliptic Curves, CNRS Lab-STICC (grant PQ-TLS
Project), advisors: A. Tisserand and K. Bigou
Former PhD Students
Publications
International Journal and Conference Articles
- M. Vollmer, K. Bigou and A. Tisserand. Using Hierarchical Approach to Speed-up RNS Base Extensions
in Homomorphic Encryption Context. Accepted in Proc. 30th IEEE Symposium on Computer
Arithmetic
(ARITH 2023), Sep. 2023 [HAL PDF].
- I.-H. Atchadam, L. Lemarchand, H. N. Tran, F. Singhoff, K. Bigou. When security affects
schedulability of TSP systems: trade-offs observed by design space exploration.
In Proc. 25th IEEE International Conference on Emerging Technologies and Factory Automation
(ETFA 2020), Sep. 2020 [IEEE Xplore][HAL]
- T. Zijlstra, K. Bigou, and A. Tisserand. FPGA Implementation and Comparison of Protections against
SCAs for RLWE. Accepted at 20th International Conference on Cryptology in India IndoCrypt 2019, Dec. 2019 [Springer Link][HAL PDF].
- L. Djath, K. Bigou and A. Tisserand. Hierarchical Approach in RNS Base Extension for Asymmetric
Cryptography. Accepted in 26th IEEE Symposium on Computer Arithmetic (ARITH 26), Jun. 2019 [IEEE Xplore] [HAL PDF].
- K. Bigou and A. Tisserand. Hybrid Position-Residues Number System. In Proc. 23rd IEEE
Symposium on Computer Arithmetic (ARITH 23), Jul.
2016 [IEEE Xplore][HAL PDF].
- K. Bigou and A. Tisserand. Single Base Modular Multiplication for Efficient Hardware RNS
Implementations of ECC. In Proc. 17th Workshop on Cryptographic
Hardware and Embedded Systems (CHES
2015), Sep. 2015
[Springer Link][HAL PDF].
- K. Bigou and A. Tisserand. RNS Modular Multiplication through Reduced Base Extensions.
In Proc. 25th IEEE International Conference on Application-specific Systems, Architectures and
Processors
(ASAP 2014), Jun. 2014 [IEEE Xplore][HAL PDF].
- K. Bigou and A. Tisserand. Improving Modular Inversion in RNS using the Plus-Minus Method.
In Proc. 15th Workshop on Cryptographic Hardware and
Embedded Systems (CHES 2013), Aug.
2013
[Springer Link] [HAL PDF]
French Conference Articles
- L. Djath, T. Zijlstra, K. Bigou and A. Tisserand. Comparaison d'algorithmes de réduction
modulaire en HLS sur FPGA. Accepted in ComPAS
2019: Conférence en Parallélisme, Architecture et Système (track
architecture), Jun. 2019 [HAL PDF].
- K. Bigou, T. Chabrier and A. Tisserand. Opérateur matériel de tests de
divisibilité par des petites constantes sur de très grands entiers. In Proc.
ComPAS 2013: Conférence en Parallélisme,
Architecture et Système (track architecture), Jan. 2013.[HAL PDF]
PhD
Summary
The main objective of this PhD thesis is to speedup elliptic curve cryptography (ECC) computations, using the
residue number system (RNS). A state-of-art of RNS for cryptographic computations is presented. Then, several
new RNS algorithms, faster than state-of-art ones, are proposed. First, a new RNS modular inversion algorithm is
presented. This algorithm leads to implementations from 5 to 12 times faster than state-of-art ones, for the
standard cryptographic parameters evaluated. Second, a new algorithm for RNS modular multiplication is proposed.
In this algorithm, computations are split into independant parts, which can be reused in some computations when
operands are reused, for instance to perform a square. It reduces the number of precomputations by 25 % and the
number of elementary multiplications up to 10 %, for some cryptographic applications (for example with the
discrete logarithm). Using the same idea, an exponentiation algorithm is also proposed. It reduces from
15 % to 22 % the number of elementary multiplications, but requires more precomputations than
state-of-art. Third, another modular multiplication algorithm is presented, requiring only one RNS base, instead
of 2 for the state-of-art. This algorithm can be used for ECC and well-chosen fields, it divides by 2 the number
of elementary multiplications, and by 4 the number of precomputations to store. Partial FPGA implementations of
our algorithm halves the area, for a computation time overhead of, at worse, 10 %, compared to state-of-art
algorithms. Finally, a method for fast multiple divisibility tests is presented, which can be used in hardware
for scalar recoding to accelerate some
ECC computations.
- K. Bigou. Étude théorique et implantation matérielle d'unités de calcul
en représentation modulaire des nombres pour la cryptographie sur courbes elliptiques.
Thèse de Doctorat, Université de Rennes 1, Novembre 2014.[HAL PDF]
Distinction
GDR ASR (Groupe De Recherche Architecture, Systèmes et Réseaux) award 2013 of the best scientific
contributions of young researchers,
section Architecture, for the work Improving Modular Inversion in RNS using the Plus-Minus
Method (given during ComPAS 2014).
Some Talk Slides
- Talk Hybrid Position-Residues Number System [PDF] at ARITH 23, Jul. 2016.
- Talk Single Base Modular Multiplication for Efficient Hardware RNS Implementations of ECC
[PDF] at CHES, Sep. 2015.
- Talk RNS Modular Arithmetic: Introduction and Cryptographic Applications [PDF] at Séminaire
sécurité des systèmes électoniques embarqués, Sep. 2015
- Talk RNS modular multiplication through reduced base extensions [PDF] at ASAP, Jun. 2014.
- Talk Improving Modular Inversion in RNS using the Plus-Minus Method [PDF] at CHES, Apr.
2013.
News and events
Conferences 2024
- Jun. : WAIFI (Ottawa, Canada )
- Jun. : ARITH (Malaga, Spain)
- Sep. : TCHES (Halifax, Canada)
https://orcid.org/0000-0001-9294-5594